1. Field of the Invention
The present invention relates to the operation of a dynamic random-access memory (DRAM) array. More specifically, the present invention relates to a method and structure for using a synchronous clock signal to control internal operations of a DRAM array.
2. Description of the Prior Art
Conventional DRAM arrays can be generally classified as being either asynchronous or synchronous. Asynchronous DRAM arrays do not use a system clock signal to control data flow to and from the array. Synchronous DRAM (SDRAM) arrays, such as the array described in Samsung's, 4Mx4 Synchronous Dynamic Random Access Memory data sheet, use a system clock signal to control data flow. Both asynchronous and synchronous DRAM arrays use a two step external operation to access the DRAM array. Each two step external operation includes a row access operation and a column access operation. The row access operation is initiated when a row access (RAS#) signal is asynchronously asserted (in an asynchronous DRAM array), or when a row access or activate command is executed (in an SDRAM array). After the row access operation is initiated, a row address is latched in the DRAM array and the data values in the selected row are loaded into a bank of sense amplifiers. The column access operation is initiated when a column access (CAS#) signal is asserted (in an asynchronous DRAM array), or when a column access command is executed (in an SDRAM array). After the column access operation is initiated, a column address is latched in the DRAM array and the data value in the selected column (sense amplifier) is accessed.
FIG. 1 is a schematic diagram of a portion of a conventional DRAM array 100. DRAM array 100 includes bit lines 1 and 2, word lines 11 and 12, memory cell transistors 21-22, memory cell capacitors 23-24, equalization line 15, equalization transistor 16, sense amplifier control lines 31-34, column switch line 35, data lines 36-37, sense amplifier transistors 40-45, column select transistors 46-47, and sense amplifier equalization transistor 51. Transistor 21 and capacitor 23 form memory cell 61 and transistor 22 and capacitor 24 form memory cell 62 as illustrated. Transistors 41-44 are connected to form regenerative latches which are used as sense amplifier 50. Sense amplifier 50 is coupled to voltage supplies V.sub.CC and ground through transistors 40 and 45, respectively.
A conventional row access operation directed toward memory cell 61 is initiated by asserting a RAS# signal. After the RAS# signal is asserted, there are a sequence of events that must occur within DRAM array 100 to successfully load the data value stored in memory cell 61 and reference cell 62 into sense amplifier 50. First, the row address must be decoded. Second, bit line equalization transistor 16 (which is normally turned on) must be turned off. Third, the selected word line 11 or 12 must be turned on. Fourth, sense amplifier 50 must be turned on. In DRAM array 100 (whether synchronous or asynchronous) the row access operation is initiated and executed as a single event in response to the RAS# signal. As a result, each of the four critical events described above must be performed in a self-timed fashion. Thus, upon receiving the RAS# signal, a delay chain launches each of the four critical events sequentially, without an external timing reference. The four critical events are described in more detail below.
The row address decoding step is performed by conventional row decoding circuitry (not shown) in response to the RAS# signal and a row address received by DRAM array 100.
When DRAM array 100 is not being accessed, bit lines 1 and 2 are equalized to a voltage equal to half of supply voltage V.sub.CC of DRAM array 100. This equalization is performed by asserting an equalization signal EQ on equalization line 15. The asserted equalization signal EQ causes equalization transistor 16 to turn on, thereby connecting bit lines 1 and 2, and forcing these bit lines 1 and 2 to approximately the same voltage. Before equalization transistor 16 is turned on, one of bit lines 1 and 2 is at V.sub.CC and the other one of bit lines 1 and 2 is at ground. Since the capacitance of bit lines 1 and 2 are approximately the same, bit lines 1 and 2 are equalized at a voltage equal to one half of supply voltage V.sub.CC when transistors 40 and 45 are turned off and equalization transistor 16 is turned on. After the RAS# signal is received, equalization transistor 16 is turned off by de-asserting the equalization signal EQ in a self-timed manner.
After equalization transistor 16 is turned off, one of word lines 11 or 12 is turned on by asserting the respective word line signal WL0 or WL1. For example, to access memory cell 61, word line signal WL0 is turned on, while word line signal WL1 remains off. Word line signal WL0 is asserted in a self-timed manner with respect to the RAS# signal. For the charge stored in cells 61 to be accurately provided to bit line 1, equalization transistor 16 must be turned off before word line 11 is turned on. When word line signal WL0 is asserted, cell transistor 21 is turned on, thereby transferring the charge stored in capacitor 23 to bit line 1. If memory cell 61 is in a charged state, the charge transfer causes the bit line signal BL on bit line 1 to have a slightly higher voltage than the bit line signal BL# on bit line 2. The larger the voltage difference between bit lines 1 and 2 before sense amplifier 50 is activated, the greater the chance that sense amplifier 50 will be able to sense the data value correctly within a shorter time period. Therefore, it is important that the differential voltage between bit lines 1 and 2 be fully developed before sense amplifier 50 is activated.
After word line 11 is turned on, sense amplifier 50 is turned on by asserting a logic low sense amplifier enable signal SA# on sense amplifier control line 31 and a logic high sense amplifier enable signal SA on sense amplifier control line 32. Sense amplifier 50 is turned on in a self-timed manner with respect to the RAS# signal. Sense amplifier enable signals SA and SA# turn on respective transistors 45 and 40, thereby applying supply voltages V.sub.CC and ground to sense amplifier 50. When DRAM array 100 is not being accessed, sense amplifier equalization transistor 51 is turned on, thereby connecting sense amplifier control lines 33 and 34 and assuring that sense amplifier 50 is reset prior to a memory access. When sense amplifier 50 is to be accessed, sense amplifier equalization transistor 51 is turned off, thereby disconnecting control lines 33 and 34, and enabling sense amplifier 50.
Prior art schemes use delay elements which allow the previously described signals to be generated at the desired intervals after the RAS# signal is received. These delay elements thereby provide the self-timing necessary to launch the four critical events. Thus, when DRAM array 100 is used in a system having a system clock signal, the data access time of DRAM memory 100 is independent of the frequency of this system clock signal. This behavior is advantageous for systems that require a relatively constant memory access time when operated over various clock frequencies. The main drawback of the previously described self-timed mode of operation, however, is that the delay elements used are subject to process, temperature and supply voltage variations. Therefore, to guarantee reliable operation over a wide range of operating conditions, the four critical events must be separated by safe timing margins, resulting in overall longer delay and slower operating speed for DRAM array 100.
It would therefore be desirable to have a structure and method for performing row access operations in a DRAM array in a manner which is faster than conventional self-timed row access operations. It would also be desirable if such a structure and method were not subject to process, temperature and supply voltage variations. It would further be desirable if such a DRAM array were capable of operating in an asynchronous manner at low frequencies for testing purposes.